Pulications

Pulications

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Books

[B2] Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor, “Understanding Logic Locking,” in Springer, 2023.

[B1] Mark Tehranipoor, Kimia Zamiri Azar, Hadi Mardani Kamali, Navid Asadizanjani, Fahim Rahman, Farimah Farahmandi, “Hardware Security: A Look into the Future,” in Springer, 2023.

Book Chapters

[BC2] Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor, “The Prospect of IP Protection via Logic Locking,” in Future of IP Protection, Springer, 2023.

[BC1] Kimia Zamiri Azar, Hadi Mardani Kamali, Avesta Sasan, “Sequential and Combinational Satisfiability Attacks,” in Encyclopedia of Cryptography, Security and Privacy (Revisited), Springer, 2022 [link].

JOURNAL PaperS

[J10] Paul E. Calzada, Md Sami Ul Islam Sami, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor, “Heterogeneous Integration Supply Chain Integrity through Blockchain and CHSM,” in ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), 2023.

[J9] Tao Zhang, Latifur Rahman, Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor, “SiPGuard: Run-time System-in-Package Security Monitoring via Power Noise Variation,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), 2023.

[J8] Mridha Md Mashahedur Rahman, Shams Tarek, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor, “Sustainability of SoC Security Monitoring: From Firmware to embedded FPGA,” in IEEE Design & Test, 2023. [link]

[J7] Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor, “Is Formal Model Checker Scalable for Security Evaluation of Logic Locking? A Semantics-based Design Space Exploration,” in IEEE Transactions on Information Forensics and Security (IEEE TIFS), 2023.

[J6] Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor, “Advances in Logic Locking: Past, Present, and Prospects,” in IACR Cryptology ePrint Archive. 2022. [link]

[J5] Kimia Zamiri Azar, Muhammad Monir Hossain, Arash Vafaei, Hasan Al Shaikh, Nurun N Mondol, Fahim Rahman, Mark Tehranipoor, Farimah Farahmandi, “Fuzz, Penetration, and AI Testing for SoC Security Verification: Challenges and Solutions,” in IACR Cryptology ePrint Archive, 2022. [link].

[J4] Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan, From Cryptography to Logic Locking: A Survey on the Architecture Evolution of Secure Scan Chains,” in IEEE Access, 2021. [link]

[J3] Kimia Zamiri Azar, Hadi Mardani Kamali, Shervin Roshanisefat, Houman Homayoun, Christos P. Sotiriou, Avesta Sasan, Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (IEEE TVLSI), 2021. [link]

[J2] Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, and Avesta Sasan, SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond The SAT Attacks,” in IACR Transactions on Cryptographic Hardware and Embedded Systems (IACR TCHES), 2019. [link]

[J1] Hadi Mardani Kamali, Kimia Zamiri Azar, and Shaahin Hessabi, DuCNoC: A High-Throughput FPGA-Based NoC Simulator Using Dual-Clock Lightweight Router Micro-Architecture,” in IEEE Transactions on Computers (IEEE TC), 2018. [link]

 

CONFERENCE papers

[C26] Nusrat Farzana, Muhammad Monir Hossain, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor, “FormalFuzzer: Formal Verification Assisted Fuzz Testing for SoC Vulnerability Detection,” in Asia and South Pacific Design Automation Conference (ASP-DAC), January, 2024.

[C25] Muhammad Monir Hossain, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor, “TaintFuzzer: SoC Security Verification using Taint Inference-enabled Fuzzing,” in International Conference On Computer Aided Design (ICCAD), November, 2023.

[C24] Hasan Al-Shaikh, Mohammad Bin Monjil, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor, Fahim Rahman, “QuardTropy: Detecting and Quantifying Unauthorized Information Leakage in Hardware Designs using g-entropy,” in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), October, 2023.

[C23] Mridha Md Mashahedur Rahman, Shams Tarek, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor, “EnSAFe: Enabling Sustainable SoC Security Auditing using eFPGA-based Accelerators,” in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), October, 2023.

[C22] Muhammad Monir Hossain, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor, “EmuFuzzer: Emulation-based Cost Function Guided Fuzzing for SoC Vulnerability Detection,” in SRC TECHCON, September, 2023.

[C21] M Sazadur Rahman, Kimia Zamiri Azar, Farimah Farahmandi, Hadi Mardani Kamali, “Metrics-to-Methods: Decisive Reverse Engineering Metrics for Resilient Logic Locking,” in ACM Great Lakes Symposium on VLSI, (GLSVLSI), June, 2023.

[C20] Upoma Das, M Sazadur Rahman, Nalla N Anandakumar, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor, “PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock Gates,” in IEEE European Test Symposium (ETS), May, 2023.

[C19] Muhammad Monir Hossain, Arash Vafaei, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor, “SoCFuzzer: SoC Vulnerability Detection using Cost Function enabled Fuzz Testing,” in Design, Automation and Test in Europe (DATE Conference), April, 2023. Nominated as Best Paper Candidate

[C18] Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor, “SheLL: Shrinking eFPGA Fabrics for Logic Locking,” in Design, Automation and Test in Europe (DATE Conference), April, 2023.

[C17] Tao Zhang, Hadi Mardani Kamali, Kimia Zamiri Azar, Mark Tehranipoor, Farimah Farahmandi, “FISHI: Fault Injection Detection in Secure Heterogeneous Integration via Power Noise Variation,” in IEEE 73rd Electronic Components and Technology Conference (ECTC), May, 2023.

[c16] Hasan Al-Shaikh, Mohammad Bin Monjil, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor, Fahim Rahman “Quantitative information Flow Analysis of Hardware designs Using Asset Flow Graphs,” in Government Microcircuit Applications & Critical Technology Conference (GoMACTeh), May, 2023.

[C15] Md Kawser Bepary, Tao Zhang, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor “EMSC-GL: Security Assessment and Modeling of electromagnetic Side-channel leakage at Gate-level,” in Government Microcircuit Applications & Critical Technology Conference (GoMACTeh), May, 2023.

[C14] Hasan Al-Shaikh, Muhammad Monir Hossain, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, “Cost Function Assisted Fuzz and Penetration Testing for SoC Security Verification,” in Government Microcircuit Applications & Critical Technology Conference (GoMACTeh), May, 2023.

[C13] Hasan Al-Shaikh, Arash Vafaei, Mridha Md Mashahedur Rahman, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor, “SHarPen: SoC Security Verification by Hardware Penetration Test,” in Asia and South Pacific Design Automation Conference (ASPDAC), January, 2023.

[C12] Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor, “Warm Up before Circuit De-obfuscation? An Exploration through Bounded-Model-Checkers,” in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), June, 2022. Recipient of the Best Poster (WiP) Award. [link]

[C11] Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan, “ChaoLock: Yet Another SAT-hard Logic Locking using Chaos Computing,” in 22nd International Symposium on Quality Electronic Design (ISQED), April, 2021. [link]

[C10] Hadi Mardani Kamali, Kimia Zamiri Azar, Shervin Roshanisefat, Ashkan Vakil, Houman Homayoun, Avesta Sasan, “ExTru: A Lightweight, Fast, and Secure Expirable Trust for the Internet of Things,” in IEEE 14th Circuits and Systems Conference (DCAS), November, 2020. Recipient of the Best Paper Award. [link]

[C9] Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan, “NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex Structures,” in International Conference On Computer Aided Design (ICCAD), November, 2020. [link]

[C8] Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan, “InterLock: An Intercorrelated Logic and Routing Locking,” in International Conference On Computer Aided Design (ICCAD), November, 2020. Nominated as Best Paper Candidate. [link]

[C7] Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan, “On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic,” in Great Lakes Symposium on VLSI (GLSVLSI), July, 2020. [link]

[C6] Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan, “SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption,” in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July, 2020.  Nominated as Best Paper Candidate. [link]

[C5] Shervin Roshanisefat, Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan, “DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain,” in IEEE VLSI Test Symposium (VTS), April, 2020. [link]

[C4] Kimia Zamiri Azar, Farnoud Farahmand, Hadi Mardani Kamali, Shervin Roshanisefat, Houman Homayoun, William Diehl, Kris Gaj, Avesta Sasan, “COMA: Communication and Obfuscation Management Architecture,” in International Symposium on Research in Attacks, Intrusions and Defenses (RAID), Beijing, China, September, 2019. [link]

[C3] Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, and Avesta Sasan, “Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks,” in Design Automation Conference (DAC), Las Vegas, NV, June, 2019. [link]

[C2] Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, and Avesta Sasan, “Threats on Logic Locking: A Decade Later,” in Great Lakes Symposium on VLSI (GLSVLSI), Tysons Corner, VA, May, 2019. [link]

[C1] Hadi Mardani Kamali, Kimia Zamiri Azar, Kris Gaj, Houman Homayoun, and Avesta Sasan, “LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection,” in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, China, August, 2018. [link]